Difference between revisions of "FOS standard cell generator from scratch"
Jump to navigation
Jump to search
| Line 24: | Line 24: | ||
* Timing of sequential cells | * Timing of sequential cells | ||
* Generate synthesis liberty file | * Generate synthesis liberty file | ||
* Capacitance extraction using a field solver (maybe FasterCap) | |||
==References== | ==References== | ||
<references /> | <references /> | ||
Revision as of 12:12, 4 February 2019
- Speaker(s): Thomas Kramer
Abstract
This talk will give an overview of automated standard cell and library synthesis and focus on the experiences made during the ongoing development of a cell generator. The core aspects consist of:
- Place & route inside the cell
- Transistor netlist generation & transistor sizing
- Cell characterization
Software
General information
- Repository: [not yet published but will come]
- Main documentation website: [not yet published, but will come]
- Wikipedia page: TBD
- Wiki page on wiki.f-si.org: TBD
Roadmap
- ✓ Place & route of single row cells
- ✓ Generate GDS
- [in progress] Generate LEF
- [in progress] Characterization
- Timing of combinatorial cells
- Timing of sequential cells
- Generate synthesis liberty file
- Capacitance extraction using a field solver (maybe FasterCap)