Difference between revisions of "Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes"

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* Speaker(s): Kirti Bhanushali
* Speaker(s): Kirti Bhanushali
* email: knbhanus@ncsu.edu  
* email: knbhanus@ncsu.edu  
* other information: xxx
* other information: www.ece.ncsu.edu


==Slides==
==Downloads==
[[Media:Dummy slide.pdf|Talk_title_name.pdf]] (to upload a file: go to Edit mode, then click on the fourth icon from the left "Embed file" and follow the instructions)
* [[:File:Slides FreePDK Kirti Bhanushali March15 2019.pdf|Slides]]
* [https://peertube.f-si.org/videos/watch/93d61de2-61b5-4b59-aeea-4337dd598f74 Video recording]


==Abstract==
==Abstract==
The design rules, layout guidelines and evolution for the open source predictive process design kit (PDK) FreePDK<big>15</big> is discussed. Additional design rules are introduced considering process variability, and challenges involved in fabrication beyond 20nm. Particularly, double patterning lithography is assumed and a unique set of design
The design rules, layout guidelines and evolution of the open source predictive process design kit (PDK) FreePDK are discussed. This talk mainly focusses on FreePDK15<sup>TM</sup> which was developed for 15nm FinFET devices and was developed in collaboration with [http://www.mentor.com MentorGraphics]. The FreePDK15 kit uses HSPICE Simulation Models from the ASU 14nm PTM-MG HP model (http://ptm.asu.edu). This talk also goes through the development of design rules and discusses the metal-stack including the use of Middle-of-line layouts used for FinFETs <ref> K. Bhanushali and W. R. Davis, "FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology", In ''Proceedings of the 2015 Symposium on International Symposium on Physical Design'' (ISPD '15), pp. 165-170.</ref> <ref> K. Bhanushali, "Design Rule Development for FreePDK15: An Open Source Predictive Process Design Kit for 15nm FinFET Devices," Masters Thesis, NCSU, 2014.</ref>. The material properties used are discussed and it is verified by use of simple/complex layouts.<ref> C. Tembe, "Layout and Parasitic Extraction for FreePDK15<sup>TM</sup>: An Open Source Predictive Process Design Kit for 15nm FinFET Devices," Masters Thesis, NCSU, 2015 </ref> The kit supports technology library and display resources for Cadence Virtuoso and Mentor Calibre DRC, LVS, and xRC rules.
rules are developed for critical dimensions. In order to improve the FinFET layout density, Middle-of-line local interconnect layers are implemented for the FinFET layout. The
rules are further validated by running Calibre design-rule checks on Virtuoso layout of an Inverter and NAND4 cells. As part of the validation process, the area of a FreePDK15
inverter was compared to the area of an inverter in 45nm bulk MOS process and the ratio was found to be 1:6. This kit primarily aims to support introduction of sub-20nm FinFET devices into research and universities.


==Software==
==Software==
===General information===
===General information===
* Repository: https://xxxx.yyy
* Repository/Download Link: https://www.eda.ncsu.edu/eda_registration.php
 
* Main documentation website: https://www.eda.ncsu.edu/wiki/FreePDK
* Main documentation website: https://www.eda.ncsu.edu/wiki/FreePDK
 
* Mailing list: If you would like to sign up to receive email alerts of design kit releases, please check out this url: https://www.eda.ncsu.edu/wiki/Ncsu-eda-announcements
* Wikipedia page: https://en.wikipedia.org/wiki/XXX-YYY-ZZZ (if a wikipedia page about the software, or a page mentioning it, does not exist yet, please consider creating one). If it gets reverted or deleted, please create a page on https://wiki.f-si.org
* Wiki page on wiki.f-si.org: https://wiki.f-si.org/index.php/XXX-YYY-ZZZ
* The software has been used in the following projects: XXX, YYY, ZZZ
 
===Roadmap===
* The software wishes to interface with the following tools: XXX, YYY
* The project seeks help on: XXX, YYY


==References==
==References==
<references />
<references />

Latest revision as of 16:44, 16 July 2019

  • Speaker(s): Kirti Bhanushali
  • email: knbhanus@ncsu.edu
  • other information: www.ece.ncsu.edu

Downloads

Abstract

The design rules, layout guidelines and evolution of the open source predictive process design kit (PDK) FreePDK are discussed. This talk mainly focusses on FreePDK15TM which was developed for 15nm FinFET devices and was developed in collaboration with MentorGraphics. The FreePDK15 kit uses HSPICE Simulation Models from the ASU 14nm PTM-MG HP model (http://ptm.asu.edu). This talk also goes through the development of design rules and discusses the metal-stack including the use of Middle-of-line layouts used for FinFETs [1] [2]. The material properties used are discussed and it is verified by use of simple/complex layouts.[3] The kit supports technology library and display resources for Cadence Virtuoso and Mentor Calibre DRC, LVS, and xRC rules.

Software

General information

References

  1. K. Bhanushali and W. R. Davis, "FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology", In Proceedings of the 2015 Symposium on International Symposium on Physical Design (ISPD '15), pp. 165-170.
  2. K. Bhanushali, "Design Rule Development for FreePDK15: An Open Source Predictive Process Design Kit for 15nm FinFET Devices," Masters Thesis, NCSU, 2014.
  3. C. Tembe, "Layout and Parasitic Extraction for FreePDK15TM: An Open Source Predictive Process Design Kit for 15nm FinFET Devices," Masters Thesis, NCSU, 2015