Difference between revisions of "Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes"

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==Abstract==
==Abstract==
The design rules, layout guidelines and evolution for the open source predictive process design kit (PDK) FreePDK<big>15</big> is discussed. Additional design rules are introduced considering process variability, and challenges involved in fabrication beyond 20nm. Particularly, double patterning lithography is assumed and a unique set of design
rules are developed for critical dimensions. In order to improve the FinFET layout density, Middle-of-line local interconnect layers are implemented for the FinFET layout. The
rules are further validated by running Calibre design-rule checks on Virtuoso layout of an Inverter and NAND4 cells. As part of the validation process, the area of a FreePDK15
inverter was compared to the area of an inverter in 45nm bulk MOS process and the ratio was found to be 1:6. This kit primarily aims to support introduction of sub-20nm FinFET devices into research and universities.


==Software==
==Software==

Revision as of 01:52, 11 March 2019


  • Speaker(s): Kirti Bhanushali
  • email: knbhanus@ncsu.edu
  • other information: xxx

Slides

Talk_title_name.pdf (to upload a file: go to Edit mode, then click on the fourth icon from the left "Embed file" and follow the instructions)

Abstract

The design rules, layout guidelines and evolution for the open source predictive process design kit (PDK) FreePDK15 is discussed. Additional design rules are introduced considering process variability, and challenges involved in fabrication beyond 20nm. Particularly, double patterning lithography is assumed and a unique set of design rules are developed for critical dimensions. In order to improve the FinFET layout density, Middle-of-line local interconnect layers are implemented for the FinFET layout. The rules are further validated by running Calibre design-rule checks on Virtuoso layout of an Inverter and NAND4 cells. As part of the validation process, the area of a FreePDK15 inverter was compared to the area of an inverter in 45nm bulk MOS process and the ratio was found to be 1:6. This kit primarily aims to support introduction of sub-20nm FinFET devices into research and universities.

Software

General information

Roadmap

  • The software wishes to interface with the following tools: XXX, YYY
  • The project seeks help on: XXX, YYY

References