View source for DRAM simulation with the simulator DRAMSys

===== Abstract =====

DRAMSys is the go-to tool for developers and engineers who need full transparency in product development with integrated DRAM subsystems. This advanced open-source simulation framework, built on the SystemC TLM-2.0 standard, delivers unmatched flexibility and performance.
DRAMSys follows a Freemium model, combining open-source accessibility with commercial options. The latest memory standards—such as DDR5, LPDDR5, and HBM3—are available through commercial models distributed by Fraunhofer IESE, with the revenue supporting ongoing maintenance and the development of future memory technologies. Universities can benefit from free academic licenses. DRAMSys is widely used in Industry, e.g. by Rambus and Ateris. With DRAMSys, you can tackle the complexities of modern memory systems effortlessly. Whether analyzing bandwidth, latency, or power consumption, DRAMSys equips you with the tools to optimize your design. This talk will provide insights and real-world use cases of DRAMSys in action.

* Speaker(s): Matthias Jung (University of Würzburg)
* email: m.jung@uni-wuerzburg.de
* Fork us on Github: https://github.com/tukl-msd/DRAMSys
* Slides: [[File:2025-07-02 FSiC25.pdf|thumb]]