Comprehensive functional verification of a configurable N-pipeline-stages RISC-V-based softcore processor using the PATARA framework

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  • Speaker: Jasper Homann, Chair for Chip Design for Embedded Computing, Technische Universität Braunschweig, Germany
  • Authors: Jasper Homann, Gia Bao Thieu, and Guillermo Payá-Vayá, Chair for Chip Design for Embedded Computing, Technische Universität Braunschweig, Germany
  • email: jasper.homann@tu-braunschweig.de

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Abstract

Compliance testing is essential when implementing the hardware architecture of a specific RISC-V instruction set. While official compliance test suites with handwritten test cases (e.g., RISC-V Foundation Architecture Test SIG[1] can aid in verification, developing a high-quality test suite demands substantial manual effort. Moreover, such test suites often lack flexibility, and they are not easily adaptable to the nuances of specific hardware implementations, such as single-cycle, multi-cycle, or pipelined architectures with varying numbers of pipeline stages. EIS-V is a RISC-V-based pipelined softcore processor with a statically configurable pipeline depth. Changing the pipeline depths introduces new types of data and control hazards into the architecture, which need to be detected by the hazard unit and resolved through forwarding or stall mechanisms. Testing the correctness of these mechanisms requires extensive test cases adapted to the specific pipeline architecture to ensure that all edge cases (e.g., all possible hazard situations, cache misses, ...) are sufficiently covered by the test suite. Instead of writing the test suites for each architecture configuration manually, comprehensive test suites fully covering all possible edge cases of each specific configuration can be generated automatically. Our previous work introduces PATARA[2][3], an open-source ISA-independent randomized test generation framework. PATARA builds on the REVERSI approach, where an instruction sequence is applied to a randomly initialized register value, and the original value is subsequently restored by executing the inverse instruction sequence. By checking if the restored value matches the original value, the processor functionality can be tested without the need for a golden reference. Additionally, the order of the instructions of the generated sequences can be scheduled to specifically test for the correct handling of, for example, data and control hazards.

This work presents early results on the verification of the configurable pipelined RV32IM EIS-V processor architecture using the PATARA framework. Up to 100% VHDL code coverage (i.e., instance, expression, and condition coverage) is reached, while the official handwritten compliance test suite can only cover up to 85% of the VHDL code.

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References

  1. ↑ https://github.com/riscv-non-isa/riscv-arch-test
  2. ↑ https://github.com/tubs-eis/PATARA
  3. ↑ Fabian Stuckmann, Pasha A. Fistanto, and Guillermo Payá-Vayá. PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores. In 10th International Conference on Modern Circuits and Systems Technologies (MOCAST). IEEE.
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