Difference between revisions of "Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?"
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==Summary== | ==Summary== | ||
This talk will explore recent advancements made in open source logic synthesis and technology mapping, and more specifically, Yosys | This talk will explore recent advancements made in open source logic synthesis and technology mapping, and more specifically, ABC (in conjunction with Yosys). | ||
It is based on the two papers referenced above. | It is based on the two papers referenced above. | ||
The first part will showcase how ABC9 was integrated into Yosys to achieve clock-rates similar to the ones by Vivado. | |||
The second part of the talk will showcase a recent implementation of mapping + retiming, which further improves achievable clock-rates. | |||
==Code== | ==Code== | ||
Revision as of 12:10, 30 June 2023
Speaker Info
- Speaker: Benjamin Barzen
- Email: bbarzen@berkeley.edu
Downloads
- 10 Minute Video introducing the talk (made originally for another conference)
- A. Mishchenko, R. Brayton, and M. Fujita, "Mapping and retiming revisited", Submitted to Proc. IWLS'23
- B.L.C. Barzen, A. Reais-Parsi, E. Hung, M. Kang, A. Mishchenko, J. W. Greene, and J. Wawrzynek, "Narrowing the synthesis gap: Academic FPGA synthesis is catching up with the industry", Proc. DATE'23
Summary
This talk will explore recent advancements made in open source logic synthesis and technology mapping, and more specifically, ABC (in conjunction with Yosys). It is based on the two papers referenced above.
The first part will showcase how ABC9 was integrated into Yosys to achieve clock-rates similar to the ones by Vivado. The second part of the talk will showcase a recent implementation of mapping + retiming, which further improves achievable clock-rates.
Code
- Repository: https://github.com/growly/date23_narrowing_the_gap
- Benchmark results: https://drive.google.com/drive/folders/1H6vDHZZXjnNIXiYPbvzaZFCulgLiR5sa?usp=drive_link