Difference between revisions of "Closing The Synthesis Gap — Is Open Source Logic Synthesis About To Beat The Industry?"
Jump to navigation
Jump to search
| Line 1: | Line 1: | ||
==Speaker Info== | |||
* Speaker: Benjamin Barzen | * Speaker: Benjamin Barzen | ||
* Email: bbarzen@berkeley.edu | * Email: bbarzen@berkeley.edu | ||
Revision as of 12:14, 28 June 2023
Speaker Info
- Speaker: Benjamin Barzen
- Email: bbarzen@berkeley.edu
Downloads
- 10 Minute Video introducing the talk (made originally for another conference)
- A. Mishchenko, R. Brayton, and M. Fujita, "Mapping and retiming revisited", Submitted to Proc. IWLS'23
- B.L.C. Barzen, A. Reais-Parsi, E. Hung, M. Kang, A. Mishchenko, J. W. Greene, and J. Wawrzynek, "Narrowing the synthesis gap: Academic FPGA synthesis is catching up with the industry", Proc. DATE'23
Summary
This talk will explore recent advancements made in open source logic synthesis and technology mapping, and more specifically, Yosys and ABC. It is based on the two papers referenced above.
Software
General information
- Repository: https://github.com/growly/date23_narrowing_the_gap
- Benchmark results: https://drive.google.com/drive/folders/1H6vDHZZXjnNIXiYPbvzaZFCulgLiR5sa?usp=drive_link