View source for Achieving Competitive Performance with Open EDA Tools on a 2MGE Open-Source Linux-Capable RISC-V SoC

* Speakers: Philippe Sauter or Thomas Benz
* email: phsauter@iis.ee.ethz.ch

==Downloads==
* [[:File:Fsic2024-pulp-basilisk.pdf|Slides.pdf]]
* [https://peertube6.f-si.org/w/p1cAaHTZY39bpaQ9pVbaXk Video recording]

==Abstract==
In this talk, we introduce Basilisk, an optimized application-specific integrated circuit implementation and design flow building on the end-to-end open-source Iguana system-on-chip (SoC). We present enhancements to synthesis tools and logic optimization scripts improving quality of results, as well as an optimized physical design with an improved power grid and cell placement integration enabling a higher core utilization. The tapeout-ready version of Basilisk implemented in IHP’s open 130 nm technology achieves an operation frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3× improvement compared to the baseline open-source electronic design automation (EDA) design flow presented in Iguana, and a higher 55 % core utilization compared to 50 % in the baseline design. Through collaboration with EDA tool developers and domain experts, Basilisk exemplifies a synergistic effort towards competitive open-source EDA tools for research and industry applications.

==Software==
===General Information===
* Basilisk chip flow: https://github.com/pulp-platform/cheshire-ihp130-o (currently on the basilisk-dev branch)
* Cheshire SoC platform: https://github.com/pulp-platform/cheshire
* SVase pre-elaborator: https://github.com/pulp-platform/svase
* ETHZ Library of Arithmetic Units: https://github.com/pulp-platform/elau

===Roadmap===
In the future we would like to again increase the complexity and size (in terms of gates) of the design.
We are happy to collaborate with anyone who thinks they could improve quality-of-results be it with another tool, flow changes or something different.

We are working on an education focused SoC (meaning smaller and easier to understand) where the students still have as much freedom as possible to change the physical design or add/change any IP they want as long as it passes a set of tests, guaranteeing a minimal set of functionality.
Here as well, we are open to collaborate with others in all stages, be it writing exercises, improving the design, improving the software side or anything related.