Difference between revisions of "65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview"
Jump to navigation
Jump to search
| Line 16: | Line 16: | ||
In order to run the whole design-flow, tools are either interacting intrinsically, or by adding some add-on graphical interfaces to increase the user-friendliness through the design-flow. | In order to run the whole design-flow, tools are either interacting intrinsically, or by adding some add-on graphical interfaces to increase the user-friendliness through the design-flow. | ||
* Digital design-flow with the different steps from RTL | * Digital design-flow with the different steps from RTL description to GDSII layout. The design-flow comes with Verilog RTL simulation, then logic synthesis, pad-ring and floor-planning, power domain network, global placement, detailed placement, fillers insertion, clock tree synthesis, global route, detail route, GDSII output. | ||
Here again, the complete design-flow from RTL to GDSII is proposed with custom scripting and graphical interfaces in order to increase the user-friendliness for a fluent flow. | Here again, the complete design-flow from RTL to GDSII is proposed with custom scripting and graphical interfaces in order to increase the user-friendliness for a fluent flow. | ||
A demonstration of these 2 design-flows on a 65nm CMOS technology is proposed. | A demonstration of these 2 design-flows on a 65nm CMOS technology is proposed. | ||
Revision as of 12:38, 5 July 2022
- Speaker: Kholdoun TORKI
- email: Kholdoun.Torki@mycmp.fr
Downloads
- Slides (to upload a file: go to Edit mode, then click on the fourth icon from the left "Embed file" and follow the instructions)
- [https:peertube.f-si.org/xxxx Video recording]
Abstract
CAD tools for making chips need a PDK (Process Design Kit) dedicated to the technology. The PDK contains technology files and device libraries. This work shows a 65nm CMOS PDK development and design-flows running on free and open-source CAD tools.
Two sections are presented:
- Full-custom design-flow showing the different steps of design at transistor level, through schematic capture, to Spice simulation, schematic driven layout, layout capture, DRC, LVS, parasitic extraction, and back-annotated simulation.
In order to run the whole design-flow, tools are either interacting intrinsically, or by adding some add-on graphical interfaces to increase the user-friendliness through the design-flow.
- Digital design-flow with the different steps from RTL description to GDSII layout. The design-flow comes with Verilog RTL simulation, then logic synthesis, pad-ring and floor-planning, power domain network, global placement, detailed placement, fillers insertion, clock tree synthesis, global route, detail route, GDSII output.
Here again, the complete design-flow from RTL to GDSII is proposed with custom scripting and graphical interfaces in order to increase the user-friendliness for a fluent flow.
A demonstration of these 2 design-flows on a 65nm CMOS technology is proposed.