65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview

• Speaker: Kholdoun TORKI
• email: Kholdoun.Torki@mycmp.fr
• Web: https://mycmp.fr

Downloads

• Slides
• Video recording
• Video 1 : Analog Simulation Demo
• Video 2 : Digital RTL to GDS design-flow Demo
• Live demo : Design flow tutorial

Abstract

CAD tools for making chips need a PDK (Process Design Kit) dedicated to the technology. The PDK contains technology files and device libraries. This work shows a 65nm CMOS PDK development and design-flows running on free and open-source CAD tools.

Two sections are presented:

• Full-custom design-flow showing the different steps of design at transistor level, through schematic capture, to Spice simulation, schematic driven layout, layout capture, DRC, LVS, parasitic extraction, and back-annotated simulation.

In order to run the whole design-flow, tools are either interacting intrinsically, or by adding some add-on graphical interfaces to increase the user-friendliness through the design-flow.

• Digital design-flow with the different steps from RTL description to GDSII layout. The design-flow comes with Verilog RTL simulation, then logic synthesis, pad-ring and floor-planning, power domain network, global placement, detailed placement, fillers insertion, clock tree synthesis, global route, detail route, GDSII output.

Here again, the complete design-flow from RTL to GDSII is proposed with custom scripting and graphical interfaces in order to increase the user-friendliness for a fluent flow.

A demonstration of these 2 design-flows is given on a 65nm CMOS technology.