Difference between revisions of "Liberty74: An Open-Source Verilog-to-PCB Flow"
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==Downloads== | ==Downloads== | ||
* [[File:Liberty74_Tobias_Senti.pdf|Slides]] | * [[:File:Liberty74_Tobias_Senti.pdf|Slides]] | ||
* [https://peertube6.f-si.org/w/1k2ciseGijFxR86ZKZcUAv Video recording] | |||
==Abstract== | ==Abstract== | ||
Latest revision as of 15:58, 1 August 2024
- Speakers: Tobias Senti
- email: talks@tsenti.li
Downloads
Abstract
With the rise of open-source EDA, creating their own chips has become more accessible. Education-oriented projects, like Tiny Tapeout, minimize the entry barrier significantly. Yet, silicon fabrication remains a complex, costly, and time-consuming process. In this talk, Liberty74 is presented, which allows digital designs to be synthesized, simulated, and implemented using discrete SMD components on PCBs. The flow exclusively uses open-source tools such as Yosys for synthesis, Verilator for simulation, and OpenROAD and KiCad for the layout of the final PCB.
Links
- Repository: https://github.com/TheMightyDuckOfDoom/liberty74