Difference between revisions of "The ACT EDA flow for asynchronous logic"
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* Speaker(s): [https://csl.yale.edu/~rajit/ Rajit Manohar] | * Speaker(s): [https://csl.yale.edu/~rajit/ Rajit Manohar] | ||
* [[File:Manohar FSiC2024.pdf|Slides]] | * Slides: [[File:Manohar FSiC2024.pdf|Slides]] | ||
==Abstract== | ==Abstract== | ||
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* Repository: https://github.com/asyncvlsi/actflow/ and https://github.com/asyncvlsi/act/ | * Repository: https://github.com/asyncvlsi/actflow/ and https://github.com/asyncvlsi/act/ | ||
* Main documentation website: https://avlsi.csl.yale.edu/act/ | * Main documentation website: https://avlsi.csl.yale.edu/act/ | ||
For those interested in learning more, we are organizing a summer school on asynchronous design. | |||
It will be held on July 1/8/15 2024. | |||
* Details: https://asyncsymposium.org/async2024/ | |||
* Registration link: https://yale.zoom.us/webinar/register/WN__GLMFmksQTqvIbXZX3h9wg | |||
===Roadmap=== | ===Roadmap=== | ||
* The software wishes to interface with the following tools: | * The software wishes to interface with the following tools: klayout | ||
* The project seeks help on: | * The project seeks help on: cell generation, detailed routing | ||
Revision as of 21:16, 12 June 2024
- Speaker(s): Rajit Manohar
- Slides: File:Manohar FSiC2024.pdf
Abstract
While asynchronous logic has shown promise for a number of problem domains, the lack of EDA support in commercial flows has made its adoption challenging. I will describe a new open-source EDA flow that takes up this challenge. We have developed a "new" design-entry language that is tailored for asynchronous design, and used it to create a true ASIC flow for asynchronous circuits. Our flow includes a static timing analysis engine capable of performance analysis as well as timing constraint checks. We use existing tools when possible, and have exports to standard formats like Verilog netlists and LEF/DEF for interoperability with other tools. We've used these tools to design numerous chips in a range of process technologies, and continue to refine the flow and improve the circuits we can generate automatically.
Software
General information
- Repository: https://github.com/asyncvlsi/actflow/ and https://github.com/asyncvlsi/act/
- Main documentation website: https://avlsi.csl.yale.edu/act/
For those interested in learning more, we are organizing a summer school on asynchronous design. It will be held on July 1/8/15 2024.
- Details: https://asyncsymposium.org/async2024/
- Registration link: https://yale.zoom.us/webinar/register/WN__GLMFmksQTqvIbXZX3h9wg
Roadmap
- The software wishes to interface with the following tools: klayout
- The project seeks help on: cell generation, detailed routing