The ACT EDA flow for asynchronous logic

• Speaker(s): Rajit Manohar

Abstract

While asynchronous logic has shown promise for a number of problem domains, the lack of EDA support in commercial flows has made its adoption challenging. I will describe a new open-source EDA flow that takes up this challenge. We have developed a new design-entry language that is tailored for asynchronous design, and used it to create a true ASIC flow for asynchronous circuits. Our flow includes a static timing analysis engine capable of performance analysis as well timing constraint checks. We use existing tools when possible, and have exports to standard formats like Verilog netlists and LEF/DEF for interoperability with other tools. We've used these tools to design numerous chips in a range of process technologies, and continue to refine the flow and improve the circuits we can generate automatically.

Software

General information

• Repository: https://github.com/asyncvlsi/actflow/ and https://github.com/asyncvlsi/act/
• Main documentation website: https://avlsi.csl.yale.edu/act/

Roadmap

• The software wishes to interface with the following tools:
• The project seeks help on: