Difference between revisions of "FSiC2025"
Jump to navigation
Jump to search
| (2 intermediate revisions by the same user not shown) | |||
| Line 13: | Line 13: | ||
==Submission== | ==Submission== | ||
This is your opportunity to present your project and to get in touch with the community. For proposing a talk, please submit a title and a short summary at fsic2025 'at' f-si.org by | This is your opportunity to present your project and to get in touch with the community. For proposing a talk, please submit a title and a short summary at fsic2025 'at' f-si.org by May 1st (third submission phase). Topics are not restricted to the tentative program. | ||
== Participation == | == Participation == | ||
| Line 24: | Line 24: | ||
== Tentative program == | == Tentative program == | ||
====Welcome==== | |||
* Gerhard Kahmen ([https://www.ihp-microelectronics.com/about-us/organization/institute-management Scientific director at IHP Microelectronics]), ''[[Welcome and introduction of IHP]]'' | |||
====High-level design and logic-synthesis==== | ====High-level design and logic-synthesis==== | ||
* Leo Moser ([https://efabless.com/ Efabless]), ''[[Greyhound: A RISC-V SoC with tightly coupled eFPGA]]'' | * Leo Moser ([https://efabless.com/ Efabless]), ''[[Greyhound: A RISC-V SoC with tightly coupled eFPGA]]'' | ||
* Edward Bingham ([https://broccolimicro.io/ Broccolimicro]), ''[[The potential for asynchronous circuits to bridge the hardware / software divide]]'' | * Edward Bingham ([https://broccolimicro.io/ Broccolimicro]), ''[[The potential for asynchronous circuits to bridge the hardware / software divide]]'' | ||
* Marcel Walter ([https://www.cda.cit.tum.de/team/ TU Munich]), ''[[aigverse: Toward Machine Learning-Driven Logic Synthesis]]'' | |||
* Tjark Petersen ([https://orbit.dtu.dk/en/persons/tjark-petersen DTU]), ''[[Towards open-source functional verification methodologies]]'' | |||
====Foundries and PDKs==== | ====Foundries and PDKs==== | ||
* Tim Edwards ([https://efabless.com/ Efabless], [http://opencircuitdesign.com/ Open Circuit Design]), ''[[IHP Open PDK integration with Magic, Netgen, and Openlane2]]'' | * Tim Edwards ([https://efabless.com/ Efabless], [http://opencircuitdesign.com/ Open Circuit Design]), ''[[IHP Open PDK integration with Magic, Netgen, and Openlane2]]'' | ||
* Jun-Ichi Okamura ([https://www.aist-solutions.co.jp/ AIST Solutions]), ''[[5W1H: Open-Source PDK from the Perspective of Japanese Foundries aka -other side of the moon-]]'' | |||
* Sergei Andreev ([https://ihp-microelectronics.com IHP Microelectronics]), ''[[IHP Open PDK: development status updates and looking ahead]]'' | |||
* Dietmar Warning ([https://ihp-microelectronics.com IHP Microelectronics]), ''[[Verilog-A models in IHP OpenPDK for a modern SiGe RF process]]'' | |||
====On-going FOS silicon projects==== | ====On-going FOS silicon projects==== | ||
| Line 38: | Line 45: | ||
* Arpad Buermen ([https://fides.fe.uni-lj.si/~arpadb/cv/cv2024.pdf University of Ljubljana]), ''[[Recent Developments in the Verilog-A Circuit Analysis Kernel]]'' | * Arpad Buermen ([https://fides.fe.uni-lj.si/~arpadb/cv/cv2024.pdf University of Ljubljana]), ''[[Recent Developments in the Verilog-A Circuit Analysis Kernel]]'' | ||
* Deni Alves ([https://deel.ufsc.br/ Federal University of Santa Catarina - Brasil]), ''[[ACM2 – A MOSFET Model Bridging Design and Simulation]]'' | * Deni Alves ([https://deel.ufsc.br/ Federal University of Santa Catarina - Brasil]), ''[[ACM2 – A MOSFET Model Bridging Design and Simulation]]'' | ||
* Volker Mühlhaus ([https://muehlhaus.com/ Mühlhaus Consulting & Software GmbH]), ''[[User friendly workflow for RFIC EM simulation using openEMS]]'' | |||
* Matthias Jung ([https://www.informatik.uni-wuerzburg.de/ce/team/matthias-jung/ University of Würzburg]), ''[[DRAM Simulation with the Simulator DRAMSys]]'' | |||
* Felix Salfelder ([https://nlnet.nl/project/Gnucap-MixedSignals/ Gnucap MixedSignals]), ''[[Progress on Verilog-AMS support in Gnucap]]'' | |||
* Tobias Kaiser ([https://www.tu.berlin/msc/ueber-uns/team/kaiser TU Berlin]), ''[[ORDeC: A text-driven analog IC design platform]]'' | |||
====Hardware security==== | ====Hardware security==== | ||
* Mattis Hasler ([https://barkhauseninstitut.org Barkhausen Institute]), ''[[A secure hardware to enable trustworthy computing]]'' | |||
====Policy, EU projects and funding opportunities==== | ====Policy, EU projects and funding opportunities==== | ||
| Line 46: | Line 58: | ||
====Economic sustainability==== | ====Economic sustainability==== | ||
* Joaquin Matres Abril, Troy Tamas, Sebastian Goeldi, Floris Laporte, Jan David Fischbach and Matthew Mckee ([https://gdsfactory.com GDSFactory]), ''[[An Open core model for EDA]]'' | |||
====Back-end design tools==== | ====Back-end design tools==== | ||
| Line 51: | Line 64: | ||
* Philippe Sauter and Thomas Benz ([https://www.ethz.ch/ ETH Zurich]), ''[[An Open-Source Power Simulation Flow using OpenROAD]]'' | * Philippe Sauter and Thomas Benz ([https://www.ethz.ch/ ETH Zurich]), ''[[An Open-Source Power Simulation Flow using OpenROAD]]'' | ||
* Christophe Alexandre ([https://github.com/xtofalex/naja Naja]), ''[[Open Source interchange format and data structures]]'' | * Christophe Alexandre ([https://github.com/xtofalex/naja Naja]), ''[[Open Source interchange format and data structures]]'' | ||
* Joaquin Matres Abril, Troy Tamas, Sebastian Goeldi, Floris Laporte, Jan David Fischbach and Matthew Mckee ([https://gdsfactory.com GDSFactory]), ''[[GDSFactory+, the all-in-one solution for chip design]]'' | |||
* Noam Cohen ([https://keplertech.io KleperTech.io]), ''[[Simplifying and Accelerating EDA Tool Development with the NajaEDA Python Library]]'' | |||
====Teaching and education==== | ====Teaching and education==== | ||
* | * Zihao Yu and Xiaoke Su ([https://ysyx.org/en/ Institute of Computing Technology, Chinese Academy of Sciences]), ''[["One Student One Chip" Initiative: Learn to Build RISC-V Chips from Scratch with MOOC]]'' | ||
* Yuchi Miao ([http://english.ict.cas.cn/ Institute of Computing Technology, Chinese Academy of Sciences]), ''[[Teaching Open Silicon Design in a Quarter]]'' | * Yuchi Miao ([http://english.ict.cas.cn/ Institute of Computing Technology, Chinese Academy of Sciences]), ''[[Teaching Open Silicon Design in a Quarter]]'' | ||
Latest revision as of 10:02, 5 April 2025
| Free Silicon Conference 2025 | |
|---|---|
 | |
| Genre | Free software and free hardware development conference |
| Location(s) | IHP Microelectronics, Frankfurt an der Oder |
| Country | Germany |
| Website | wiki.f-si.org/index.php/FSiC2025 |
The 2025 Free Silicon Conference (FSiC) will take place at IHP Microelectronics (Frankfurt an der Oder) on July 2, 3, 4 2025 (Wednesday to Friday). This event will build on top of the past FSiC editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification.
Submission
This is your opportunity to present your project and to get in touch with the community. For proposing a talk, please submit a title and a short summary at fsic2025 'at' f-si.org by May 1st (third submission phase). Topics are not restricted to the tentative program.
Participation
To participate to the conference, both as speaker and as attendee, it is necessary to register here.
From this year we have introduced a ticket:
- for non-profit, enthusiasts, free-time contributors: free admission
- for affiliated students: early bird 160 €, regular 200 €
- for professionals: early bird 340 €, regular 400 €
Tentative program
Welcome
- Gerhard Kahmen (Scientific director at IHP Microelectronics), Welcome and introduction of IHP
High-level design and logic-synthesis
- Leo Moser (Efabless), Greyhound: A RISC-V SoC with tightly coupled eFPGA
- Edward Bingham (Broccolimicro), The potential for asynchronous circuits to bridge the hardware / software divide
- Marcel Walter (TU Munich), aigverse: Toward Machine Learning-Driven Logic Synthesis
- Tjark Petersen (DTU), Towards open-source functional verification methodologies
Foundries and PDKs
- Tim Edwards (Efabless, Open Circuit Design), IHP Open PDK integration with Magic, Netgen, and Openlane2
- Jun-Ichi Okamura (AIST Solutions), 5W1H: Open-Source PDK from the Perspective of Japanese Foundries aka -other side of the moon-
- Sergei Andreev (IHP Microelectronics), IHP Open PDK: development status updates and looking ahead
- Dietmar Warning (IHP Microelectronics), Verilog-A models in IHP OpenPDK for a modern SiGe RF process
On-going FOS silicon projects
- Simon Dorrer (Johannes Kepler University (JKU) Linz), Design of an Open-Source Fully-Differential Adaptive Event-Based ADC for Bio-Signal Acquisition in 130nm CMOS
Analog flow, transistor modelling and circuit simulation
- Arpad Buermen (University of Ljubljana), Recent Developments in the Verilog-A Circuit Analysis Kernel
- Deni Alves (Federal University of Santa Catarina - Brasil), ACM2 – A MOSFET Model Bridging Design and Simulation
- Volker Mühlhaus (Mühlhaus Consulting & Software GmbH), User friendly workflow for RFIC EM simulation using openEMS
- Matthias Jung (University of Würzburg), DRAM Simulation with the Simulator DRAMSys
- Felix Salfelder (Gnucap MixedSignals), Progress on Verilog-AMS support in Gnucap
- Tobias Kaiser (TU Berlin), ORDeC: A text-driven analog IC design platform
Hardware security
- Mattis Hasler (Barkhausen Institute), A secure hardware to enable trustworthy computing
Policy, EU projects and funding opportunities
Standards
Economic sustainability
- Joaquin Matres Abril, Troy Tamas, Sebastian Goeldi, Floris Laporte, Jan David Fischbach and Matthew Mckee (GDSFactory), An Open core model for EDA
Back-end design tools
- Mohamed Gaber (The American University in Cairo), OpenLane: Looking to the Future
- Philippe Sauter and Thomas Benz (ETH Zurich), An Open-Source Power Simulation Flow using OpenROAD
- Christophe Alexandre (Naja), Open Source interchange format and data structures
- Joaquin Matres Abril, Troy Tamas, Sebastian Goeldi, Floris Laporte, Jan David Fischbach and Matthew Mckee (GDSFactory), GDSFactory+, the all-in-one solution for chip design
- Noam Cohen (KleperTech.io), Simplifying and Accelerating EDA Tool Development with the NajaEDA Python Library
Teaching and education
- Zihao Yu and Xiaoke Su (Institute of Computing Technology, Chinese Academy of Sciences), "One Student One Chip" Initiative: Learn to Build RISC-V Chips from Scratch with MOOC
- Yuchi Miao (Institute of Computing Technology, Chinese Academy of Sciences), Teaching Open Silicon Design in a Quarter
- Philippe Sauter and Thomas Benz (ETH Zurich), ArtistIC: An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
Lighting talks
- Zachary Kohnen and Alex Alvarado (Eindhoven University of Technology), Manchester decoder of a home thermostat's wireless protocol in the Tiny Tapeout 07 shuttle
Organizing committee
‟For democracy to thrive, technology must empower, not control.”
‟Technology is political. I stand for defending free access to technology and the right for transparency.”
‟Free and transparent technology empowers people and protects fundamental freedoms.”
Constantin Gierczak-Galle
Student and enthousiast
‟Technology can be both Mankind's development and demise. Promoting the former while hindering the latter can only happen through decentralization, democratization and open collaboration.”
‟I am passionate about helping people with my technical skills. Coding EDA is like gardening to me: may it grow and feed people.”
‟I like to understand technology, to adapt and enhance it. Technology should not be mythical or owned by experts only, it needs to be comprehensible.”
‟Open-source tools and technology gives freedom to students to explore chip design on their own and on their computers, not limiting them to the walled garden of a dedicated lab at the University.”
‟Our goal is to make open source EDA tools and design flows easily accessible and usable for anyone who wants to get into ASIC chip design, test new design ideas and develop them to a manufacturable level.”
Local hosting committee
The event is supported by members of IHP Microelectronics including Kerstin Kaslack, Jonas Linzert, Henriette Mohles, Anna Sojka-Piotrowska and Inesa Posypai.
Donations
We are looking for sponsors to cover extra services at the conference. In case of interest, please see the registration tab here.
Sponsors
Acknowledgements
This conference is co-funded by European Union through the Coordination and Support Action GoIT project with ID number 101070669. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or of the European Commission. Neither the European Union nor the European Commission can be held responsible for them.
This conference also received funding from the Swiss State Secretariat for Education, Research and Innovation (SERI) under the NGI0 Commons Fund project. The NGI0 Commons Fund has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No. 101135429.
