Open-Source Verification of Digital ASIC/FPGA Circuits

• Speakers: Stefano Minigutti (SyoSil)
• email: stefano@syosil.com
• website: https://www.syosil.com/

Downloads

• Slides
• Video recording

Abstract

Even though the methods for designing synchronous semiconductor devices like ASICs and FPGAs fundamentally remain unchanged for more than 25 years, the methods used verification of such designs have evolved rapidly, from writing simple directed tests towards massive coverage driven constrained random verification, as well as formal property checking of assertions (temporal logic).

Initially, these changes were driven by proprietary Closed-Source languages, running on commercial and expensive tooling, only available to exclusive engineering teams. Later such languages converged towards IEEE standardization, allowing interoperability across tools that stayed commercial, but still required massive investments in tooling. Especially ASIC/FPGA development teams have been unable to join this massive push of technology, still forced to write directed tests for verification.

Lately it seems the ASIC/FPGA engineering world finally benefits from the Open-Source revolution known from software development. Languages and libraries shift towards languages known from Open-Source (e.g. Python), and employment methods of these with Open-Source available tooling now finally allows a complete change.

This presentation will focus on:

• Used UVM libraries in python.
• Used Open-source simulation’s tools.
• Implementation of a UVM testbench using python UVM:
  • Vertical reuse
  • Randomization
  • Coverage collection and report
  • Reference model
  • Differences and limitations compared to SV version
• Open-Source advantages
• Road ahead

Software

General information

• Repository: TB_example_GitHub
• White paper: OSV Whitepaper