Difference between revisions of "OpenRAM: An Open-Source Memory Compiler"
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* Speaker: Matthew Guthaus | * Speaker: Matthew Guthaus | ||
* Email: mrg@ucsc.edu | * Email: mrg@ucsc.edu | ||
* Other information: https://vlsida.soe.ucsc.edu/ | * Other information: https://vlsida.soe.ucsc.edu/ | ||
== | == Downloads == | ||
[[ | * [[:File:OpenRAM FSiC2019.pdf|Slides]] | ||
* [https://peertube.f-si.org/videos/watch/654c6563-a553-4351-81d3-76e3943e5c9a Video recording] | |||
== Abstract == | == Abstract == | ||
[https://github.com/VLSIDA/OpenRAM OpenRAM] is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies. | [https://github.com/VLSIDA/OpenRAM OpenRAM] is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies. | ||
| Line 14: | Line 13: | ||
===General information=== | ===General information=== | ||
* Repository: https://vlsida.github.io/OpenRAM/ https://github.com/VLSIDA/OpenRAM | * Repository: https://vlsida.github.io/OpenRAM/ https://github.com/VLSIDA/OpenRAM | ||
* Main documentation website: [https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing| | * Main documentation website: [https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing|Documentation] | ||
* Wikipedia page: | * Wikipedia page: missing | ||
===Roadmap=== | ===Roadmap=== | ||
Latest revision as of 16:48, 16 July 2019
- Speaker: Matthew Guthaus
- Email: mrg@ucsc.edu
- Other information: https://vlsida.soe.ucsc.edu/
Downloads
Abstract
OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.
Software
General information
- Repository: https://vlsida.github.io/OpenRAM/ https://github.com/VLSIDA/OpenRAM
- Main documentation website: [1]
- Wikipedia page: missing
Roadmap
- The project seeks help on: FinFET memories, Designer Feedback, Other types of memories (CAMs, RFs, etc.)
References
- B. Wu, J. Stine, M. R. Guthaus, ``Fast and Area-Efficient Word-Line Driver Topology Optimization, International Symposium on Circuits and Systems (ISCAS), 2019
- M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016
- S. Ataei, J. Stine, M. Guthaus, “A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS,” International Conference on Computer Design (ICCD), 2016, pp. 499-506.
- E. Ebrahimi, M. Guthaus, J. Renau, “Timing Speculative SRAM”, IEEE In- ternational Symposium on Circuits and Systems (ISCAS), 2017