Difference between revisions of "OpenRAM: An Open-Source Memory Compiler"
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== Slides == | == Slides == | ||
[[ | [[Media:OpenRAM FSiC2019.pdf]] | ||
== Abstract == | == Abstract == | ||
Revision as of 21:51, 11 March 2019
- Speaker: Matthew Guthaus
- Email: mrg@ucsc.edu
- Other information: https://vlsida.github.io/OpenRAM/ https://github.com/VLSIDA/OpenRAM
Slides
Abstract
OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.
Software
General information
- Repository: https://vlsida.github.io/OpenRAM/ https://github.com/VLSIDA/OpenRAM
- Main documentation website: Documentation
- Wikipedia page:
- Wiki page on wiki.f-si.org: https://wiki.f-si.org/index.php/XXX-YYY-ZZZ
Roadmap
- The project seeks help on: FinFET memories, Designer Feedback, Other types of memories (CAMs, RFs, etc.)