The Raven chip: First-time silicon success with qflow and efabless

From F-Si wiki
Jump to: navigation, search

Slides

File:Qflow Raven FSiC2019.pdf

Abstract

The Raven chip is a proof-of-concept ASIC and reference design created on the efabless design platform using all open-source EDA tools. In addition to using open-source tools, the Raven chip itself is open source in hardware, software, and firmware. Open source layout is made possible by the use of tools such as qflow, magic, and netgen, and the use of abstracted views of core components. By presenting a viewable layout of the reference design and making available all the tools and documentation needed to create and validate it, the process of making a custom microprocessor can be accomplished by a single person in a matter of weeks. To complete the proof-of-concept, the Raven chip was manufactured on X-Fab XH018 and tested, and successfully operates at a core clock rate of 100MHz.

Software

General information

Roadmap

  • The software wishes to interface with the following tools: abk-openroad, coriolis
  • The project seeks help on: IR drop analysis, electromigration analysis, dynamic power estimation

References