Pages without language links

Jump to navigation Jump to search

The following pages do not link to other language versions.

Showing below up to 50 results in range #1 to #50.

View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)

  1. ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals
  2. ASICone. Goals, timeline, participants and tools
  3. CERN OHL v2 draft
  4. CERN Open Hardware License (OHL)
  5. CIAN Team Welcome
  6. CMOS functional abstraction
  7. CMP add on services - Towards Foundry PDKs on Free CAD Tools
  8. Converting 45nm transistor netlists to open standards
  9. Coriolis (installation)
  10. Coriolis (tutorials)
  11. Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes
  12. F-Si Donations
  13. F-Si Statute
  14. FOS standard cell generator from scratch
  15. FSiC2019
  16. FSiC2019 reimbursement
  17. FSiC2019 venue
  18. FSiC2020
  19. FSiC2021
  20. From CMOS transistors to filters - A library of analog schematics with automated sizing
  21. From filters to CMOS transistors - A library of analog schematics with automated sizing
  22. From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD
  23. GAUT
  24. GAUT - A Free and Open-Source High-Level Synthesis tool
  25. GHDL and the economy of EDA FOSS
  26. GnuCap: Progress and Opportunities
  27. Gnu Circuit Analysis Package (GnuCap)
  28. Guidelines for invited speakers
  29. Hands-on with KLayout: Design rule checks and layout to netlist tools
  30. High level Simulation
  31. High level system modelling, hands-on computer session
  32. KLayout's deep verification base project
  33. LIP6 Welcome
  34. Lesson learned from Retro-uC and the search for the ideal EDA flow for open source silicon
  35. LibrEDA
  36. LibreCell
  37. Libre Silicon Compiler
  38. LiteX: an open-source SoC builder and library based on Migen Python DSL
  39. Main Page
  40. Main Page/Software
  41. Matthias:UnsortedThroughsOnFOSSForEDA
  42. Mediawiki template for invited speakers
  43. Mixed-signal system modelling and simulation
  44. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design
  45. Need for a free alternative to OpenAccess (by Matthias)
  46. Ngspice - an open source mixed signal circuit simulator
  47. OpenRAM: An Open-Source Memory Compiler
  48. Open Source Parasitic Extraction
  49. Open Source in Healthcare, an hardware approach: the echOpen project case
  50. Placement algorithms for standard cells in Coriolis

View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)