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Showing below up to 50 results in range #1 to #50.

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  1. (hist) ‎Statute of the Free Silicon Foundation (I) ETS ‎[35,187 bytes]
  2. (hist) ‎High level system modelling, hands-on computer session ‎[24,004 bytes]
  3. (hist) ‎White paper for the EC, January 2020 ‎[20,934 bytes]
  4. (hist) ‎Standard-cell characterization ‎[16,183 bytes]
  5. (hist) ‎FSiC2023 ‎[13,400 bytes]
  6. (hist) ‎FSiC2022 ‎[13,360 bytes]
  7. (hist) ‎KiCad ‎[11,255 bytes]
  8. (hist) ‎FSiC2019 ‎[11,221 bytes]
  9. (hist) ‎Open Source Parasitic Extraction ‎[8,445 bytes]
  10. (hist) ‎Recommendations for the EC on how to reduce the environmental impact of the ICT sector ‎[7,632 bytes]
  11. (hist) ‎FSiC2024 ‎[6,976 bytes]
  12. (hist) ‎F-Si Statute ‎[6,568 bytes]
  13. (hist) ‎Standard-cell synthesis ‎[6,553 bytes]
  14. (hist) ‎Recommendations and roadmap for the development of open-source silicon in the EU ‎[5,411 bytes]
  15. (hist) ‎FSiC2022 venue ‎[4,571 bytes]
  16. (hist) ‎Need for a free alternative to OpenAccess (by Matthias) ‎[3,970 bytes]
  17. (hist) ‎From filters to CMOS transistors - A library of analog schematics with automated sizing ‎[3,892 bytes]
  18. (hist) ‎Physical security for cryptographic implementations with open hardware ‎[3,822 bytes]
  19. (hist) ‎The importance of EU Academia in developing the chips of the future ‎[3,552 bytes]
  20. (hist) ‎Matthias:UnsortedThroughsOnFOSSForEDA ‎[3,355 bytes]
  21. (hist) ‎Merging Gnucap and Qucs -- The Why and How ‎[3,157 bytes]
  22. (hist) ‎SystemC AMS and upcoming free frameworks for the free design ‎[2,967 bytes]
  23. (hist) ‎High level Simulation ‎[2,916 bytes]
  24. (hist) ‎CMP add on services - Towards Foundry PDKs on Free CAD Tools ‎[2,913 bytes]
  25. (hist) ‎FOS standard cell generator from scratch ‎[2,671 bytes]
  26. (hist) ‎FSiC2023 venue ‎[2,632 bytes]
  27. (hist) ‎Open-source electronic design automation for agile network defense at OVHcloud ‎[2,555 bytes]
  28. (hist) ‎Hands-on with KLayout: Design rule checks and layout to netlist tools ‎[2,540 bytes]
  29. (hist) ‎The development of the NSXLIB standard cell scalable library ‎[2,529 bytes]
  30. (hist) ‎KLayout XSection tool - Deep insights or nonsense in colors? ‎[2,351 bytes]
  31. (hist) ‎Guidelines for invited speakers ‎[2,237 bytes]
  32. (hist) ‎Coriolis (installation) ‎[2,232 bytes]
  33. (hist) ‎Horizon 2021 Coordination and Support Action (CSA) proposal ‎[2,186 bytes]
  34. (hist) ‎Proof-of-concept for scalable analog blocks using the PDKMaster framework ‎[2,164 bytes]
  35. (hist) ‎KQCircuits – open-source EDA software for designing chips with super conducting qubits ‎[2,158 bytes]
  36. (hist) ‎Inclusive Modeling with SysMD ‎[2,143 bytes]
  37. (hist) ‎Mediawiki template for invited speakers ‎[2,082 bytes]
  38. (hist) ‎Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ‎[2,058 bytes]
  39. (hist) ‎Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes ‎[2,043 bytes]
  40. (hist) ‎FSiC2019 venue ‎[1,982 bytes]
  41. (hist) ‎Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana ‎[1,950 bytes]
  42. (hist) ‎Environmental impacts of electronics and the role of open source hardware ‎[1,879 bytes]
  43. (hist) ‎E-Waste Reverse Engineering Toolkit (RET) ‎[1,844 bytes]
  44. (hist) ‎65nm CMOS Design-Flows on Free and Open-Source Tools : An Overview ‎[1,835 bytes]
  45. (hist) ‎The Raven chip: First-time silicon success with qflow and efabless ‎[1,824 bytes]
  46. (hist) ‎Open source Design Flow status and roadmap for IHP BiCMOS technology ‎[1,823 bytes]
  47. (hist) ‎Converting 45nm transistor netlists to open standards ‎[1,798 bytes]
  48. (hist) ‎OpenRAM: An Open-Source Memory Compiler ‎[1,792 bytes]
  49. (hist) ‎Toward a collaborative environment for Open Hardware Design ‎[1,735 bytes]
  50. (hist) ‎Tutorial and FAQ on physical verification, DRC+LVS ‎[1,728 bytes]

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