Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design

From F-Si wiki
Jump to: navigation, search
  • Speaker(s): Daniela Genius
  • email:
  • Sorbonne Université, LIP6


The design methodology of an embedded system should start with a system-level partitioning dividing functions into hardware and software. However, since this partitioning decision is taken at a high level of abstraction, we propose regularly validating the selected partitioning during software development. We introduce a new model-based engineering process with a supporting toolkit, first performing system-level partitioning, and then assessing the partitioning choices thus obtained at different levels of abstraction during software design. This assessment shall in particular validate the assumptions made on system-level (e.g. on cache miss rates) that cannot be precisely determined without low-level hardware model. This sequence of partitioning and prototyping serves two purposes: validating the assumptions made on system-level, and, while developing the software, taking into account the problematic cases (bus congestion, ping-pong caches etc.) which cannot be detected without precisely simulating the underlying hardware. High-level partitioning simulations/verification rely on custom model-checkers and abstract models of software and hardware, while low-level prototyping simulations rely on automatically generated C-POSIX software code executing on a cycle-precise virtual prototyping platform. An automotive case study on an automatic braking application illustrates our complete approach.


General information


  • The software wishes to interface with the following tools: SystemC AMS