https://wiki.f-si.org/api.php?action=feedcontributions&user=Coussy&feedformat=atomF-Si wiki - User contributions [en]2024-03-29T08:36:52ZUser contributionsMediaWiki 1.36.1https://wiki.f-si.org/index.php?title=File:Fsic-coussy.pdf&diff=1978File:Fsic-coussy.pdf2019-03-14T09:05:30Z<p>Coussy: Coussy uploaded a new version of File:Fsic-coussy.pdf</p>
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<div></div>Coussyhttps://wiki.f-si.org/index.php?title=GAUT_-_A_Free_and_Open-Source_High-Level_Synthesis_tool&diff=1977GAUT - A Free and Open-Source High-Level Synthesis tool2019-03-14T08:44:43Z<p>Coussy: </p>
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<div>* Speaker(s): Philippe Coussy<br />
* email: philippe.coussy@univ-ubs.fr<br />
* web: http://www-labsticc.univ-ubs.fr/~coussy/<br />
<br />
==Slides==<br />
[[File:Fsic-coussy.pdf|thumb|Slides]]<br />
==Abstract==<br />
GAUT is a free academic High-Level Synthesis (HLS) tool. Starting from a C/C++ input description and a set of synthesis options, GAUT automatically generates a hardware architecture composed of a controller and a datapath as well as memory and communication interfaces. GAUT generates IEEE P1076 compliant RTL level VHDL and SystemC projects. The VHDL files are inputs for off the shelf logical synthesis tools. Windows, Linux and MacOS platforms are supported (32 or 64 bits).<br />
<br />
This talk will introduce the main steps of HLS and give an overview of the GAUT tool (main features, architecture, short history and purpose).<br />
<br />
<br />
<br />
More information are available on-line [http://www.gaut.fr here]</div>Coussyhttps://wiki.f-si.org/index.php?title=File:Fsic-coussy.pdf&diff=1976File:Fsic-coussy.pdf2019-03-14T08:38:18Z<p>Coussy: </p>
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<div></div>Coussyhttps://wiki.f-si.org/index.php?title=GAUT_-_A_Free_and_Open-Source_High-Level_Synthesis_tool&diff=1802GAUT - A Free and Open-Source High-Level Synthesis tool2019-03-06T08:01:26Z<p>Coussy: </p>
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<div>GAUT is a free academic High-Level Synthesis (HLS) tool. Starting from a C/C++ input description and a set of synthesis options, GAUT automatically generates a hardware architecture composed of a controller and a datapath as well as memory and communication interfaces. GAUT generates IEEE P1076 compliant RTL level VHDL and SystemC projects. The VHDL files are inputs for off the shelf logical synthesis tools. Windows, Linux and MacOS platforms are supported (32 or 64 bits).<br />
<br />
This talk will introduce the main steps of HLS and give an overview of the GAUT tool (main features, architecture, short history and purpose).<br />
<br />
More information are available on-line [http://www.gaut.fr here]</div>Coussyhttps://wiki.f-si.org/index.php?title=FSiC2019&diff=1801FSiC20192019-03-06T08:00:02Z<p>Coussy: /* High-level digital design (session I) */</p>
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<div>{{Infobox recurring event<br />
|name = Free Silicon Conference 2019<br />
|logo = fsic2019_logo.svg<br />
|genre = Free software and free hardware development conference<br />
|location = Paris, Sorbonne Université<br />
|country = France<br />
|website = [https://wiki.f-si.org/index.php/FSiC2019 wiki.f-si.org/index.php/FSiC2019]<br />
}}<br />
The [https://www-soc.lip6.fr/events/pastevents/2018/ second] '''Free Silicon Conference (FSiC)''' will be held at [https://www-soc.lip6.fr/evenements/ Sorbonne Université] (Paris) on '''March 14-16 2019'''. The conference will bring together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. The conference consists of three full days, including a Saturday for facilitating those who are involved as non-professionals. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon''].<br />
<br />
== Participation ==<br />
Attending the conference is free of charge. Lunches, dinners and drinks will be offered. However, due to the limited number of spaces available, seats must be reserved before February *21* by writing at fsic2019 'at' f-si.org.<br />
<br />
The submission window closed on January 31 2019.<br />
<br />
== Organizing committee ==<br />
* Marie-Minerve Louërat, Lip6, CNRS<br />
* Roselyne Chotin, Lip6, Sorbonne Université<br />
* Jean-Paul Chaput, Lip6, Sorbonne Université<br />
* Luca Alloatti, ETH-Zurich<br />
* Matthias Koefferlein, KLayout project<br />
* Sean Cross, Kosagi<br />
* Thomas Kramer, ETH-Zurich<br />
<br />
==Conference program==<br />
<br />
=== March 14, Thursday (Day 1) ===<br />
==== Registration ====<br />
* 9:00-9:30, Registration and coffee<br />
<br />
==== Welcome ====<br />
* 9:35-9:45, [https://www.lip6.fr/presentation/directeur.php?LANG=en LIP6] Director [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P182 Fabrice Kordon]<br />
* 9:45-9:50, [https://www-soc.lip6.fr/en/team-cian/ CIAN team] within LIP6<br />
* 9:50-9:55, Welcome from the Free Silicon Foundation<br />
<br />
==== Introduction and motivation for Free and Open Source (FOS) silicon ====<br />
* 10:00-10:30, [https://puri.sm/about/team/ Todd Weaver], ''Title to be announced'', [https://puri.sm Purism]<br />
* 10:30-11:00, [https://www.cs.hs-rm.de/~reith/ Steffen Reith], ''[[Towards digital sovereignty by open source (hardware)]]'', [https://www.hs-rm.de/ Hochschule RheinMain]<br />
<br />
====High-level digital design (session I)====<br />
* 11:00-11:30, [http://www-labsticc.univ-ubs.fr/~coussy/ Philippe Coussy], ''[[GAUT - A Free and Open-Source High-Level Synthesis tool]]'', [http://www.gaut.fr/ GAUT], Lab-STICC Université Bretagne Sud<br />
* 11:30-12:00, Tristan Gingold, ''[[GHDL and the economy of EDA FOSS]]'', [http://ghdl.free.fr/ GHDL]<br />
* 12:00-12:30, Frédéric Pétrot, ''[[High level Simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]<br><br><br />
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br><br />
* 13:30-14:00, Daniela Genius, ''[[Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design ]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P96 Sorbonne Université, LIP6]<br />
* 14:00-14:30, Charles Papon, ''[[From the RISC-V spec to a low-tech SoC, passing by SpinalHDL, VexRiscv and OpenOCD]]'', [https://github.com/SpinalHDL SpinalHDL]<br />
* 14:30-15:00, Jean Bruant, ''[[State of the art on high-level hardware description languages to generate VHDL or SystemVerilog]]'', [https://www.ovh.com/fr/ OVH] and [http://tima.imag.fr/sls/ TIMA Laboratory]<br />
<br />
====Mixed-signal/analog design and transistor modelling====<br />
* 15:00-15:30, Christoph Grimm, ''[[SystemC AMS and upcoming free frameworks for the free design]]'', [https://cps.cs.uni-kl.de/en/staff/christoph-grimm-prof-dr/ Kaiserslautern University]<br />
* 15:30-16:00, Liliana Andrade, ''[[Mixed-signal system modelling and simulation]]'', [http://tima.imag.fr/sls/ Université Grenoble Alpes and TIMA Laboratory]<br><br><br />
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br><br />
* 16:30-17:00, [https://www.uni-due.de/person/1998 Holger Vogt], ''[[ngspice - an open source mixed signal circuit simulator]]'', [http://ngspice.sourceforge.net/ ngspice], [http://www.uni-due.de/ebs University Duisburg-Essen]<br />
* 17:00-17:30, Al Davis, ''[[Gnu Circuit Analysis Package (GnuCap)]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]<br />
* 17:30-18:00, Felix Salfelder, ''[[GnuCap: Progress and Opportunities]]'', [https://savannah.gnu.org/git/?group=gnucap GnuCap]<br />
* 18:00-18:30, [http://www.mos-ak.org/wg.html Wladek Grabinski], ''[[MOS-AK FOSS TCAD/EDA Perspective]]'', [http://mos-ak.org/ MOS-AK (EU)]<br />
<br />
====Evening program "beer & baguette" at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']====<br />
* 19:00-22:00: drinks are served<br />
* 19:30: dinner is served<br />
* 22:30: end of the day<br />
<br />
=== March 15, Friday (Day 2) ===<br />
==== Morning Coffee ====<br />
* 8:30-9:00, Early bird coffee and tea<br />
<br />
==== Impact of FOS hardware ====<br />
* 9:00-9:30, Olivier de Fresnoye, ''[[Open Source in Healthcare, an hardware approach: the echOpen project case]]'', [http://www.echopen.org/ echopen]<br />
* 9:30-10:00, Edmund Humenberger, ''[[ASICone. Goals, timeline, participants and tools]]'', [https://www.symbioticeda.com Symbiotic EDA]<br />
* 10:00-10:30, Staf Verhaegen, ''[[Lesson learned from Retro-uC and search for ideal HDL for open source silicon]]''<br />
<br />
====Foundries, PDKs and cell libraries====<br />
* 10:30-11:00, Jean-Christophe Crébier, ''[[CMP add on services]]'', [https://mycmp.fr/ CMP]<br />
* 11:00-11:30, Kirti Bhanushali, ''[[Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes]]'', [https://www.eda.ncsu.edu/wiki/FreePDK NCSU, FreePDK]<br />
* 11:30-12:00, Thomas Benz, ''[[Converting 45nm transistor netlists to open standards]]'', [https://www.ethz.ch ETH Zurich]<br />
* 12:00-12:30, Naohiko Shimizu, ''[[The development of the NSXLIB standard cell scalable library]]'', [http://labo.nshimizu.com/ Tokai University]<br><br><br />
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br><br />
* 13:30-14:00, Hagen Sankowski, ''[[Popcorn - or how many cells your Standard Cell Library has?]]'', [http://libresilicon.com/ LibreSilicon]<br />
* 14:00-14:30, [https://www.soe.ucsc.edu/people/mrg Matthew Guthaus], ''[[OpenRAM]]'', [https://openram.soe.ucsc.edu/ OpenRAM, UCSC]<br />
* 14:30-15:00, Thomas Kramer, ''[[FOS standard cell generator from scratch]]'', [https://www.ethz.ch ETH Zurich]<br />
<br />
====Back-end flow and algorithms====<br />
* 15:00-15:30, Gabriel Gouvine, ''[[Placement algorithms for standard cells in Coriolis]]'', [https://www.localsolver.com/ Local Solver]<br />
* 15:30-16:00, Matthias Köfferlein, ''[[KLayout's deep verification base project]]'', [https://klayout.de KLayout]<br><br><br />
* '''16:00-16:30''', '''Afternoon break.''' Coffee is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br><br><br />
* 16:30-17:00, Pirouz Bazargan Sabet, ''[[Functional abstraction]]'', [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P87 Sorbonne Université and LIP6 Laboratory]<br />
* 17:00-17:30, Enrico Di Lorenzo, [[Open_Source_Parasitic_Extraction|''Open Source parasitic extraction - solutions, challenges, and business models'']], [http://www.fastfieldsolvers.com FastFieldSolvers]<br />
* 17:30-18:00, Tim Edwards, ''[[The Raven chip: First-time silicon success with qflow and efabless]]'', [http://opencircuitdesign.com/ Open Circuit Design, Qflow]<br />
* 18:00-18:30, Andreas Westerwick, ''[[Libre Silicon Compiler]]'', [http://libresilicon.com/ LibreSilicon] <br />
* 18:30-19:00, Hagen Sankowski, ''[[Somebody is using the Advanced Library Format (ALF)? We like to do!]]'', [http://libresilicon.com/ LibreSilicon]<br />
<br />
====High-level digital design (session II)====<br />
* 18:30-19:00, Florent Kermarrec, ''[[LiteX: an open-source SoC builder and libraty based on Migen Python DSL]]'', [http://enjoy-digital.fr/ Enjoy Digital]<br />
<br />
====Evening program "beer & baguette" at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/caves_esclangon.html ''caves Esclangon'']====<br />
* 19:00-22:00: drinks are served<br />
* 19:30: dinner is served<br />
* 22:30: end of the day<br />
<br />
=== March 16, Saturday (Day 3) ===<br />
==== Morning Coffee ====<br />
* 8:30-9:00, Early bird coffee and tea<br />
<br />
====Licenses====<br />
* 9:00-9:30, Tristan Gingold, ''[[CERN OHL v2 draft]]'', [https://www.ohwr.org/project/cernohl/wikis/CERN-OHL-v2-draft CERN]<br />
<br />
====High-level digital design (session III)====<br />
* 9:30-10:00, Guillaume Delbergue, ''[[Toward a collaborative environment for Open Hardware Design]]'', [https://www.hiventive.com/ Hiventive]<br />
* 10:00-11:00, Mark Burton, ''[[High level system modelling, hands-on computer session]]'', [https://www.greensocs.com/about-us GreenSocs], '''(Tutorial)'''<br />
<br />
====Analog back-end design====<br />
* 11:00-11:30, Abhaya Chandra Kammara, ''[[ABSYNTH: Analog Design Automation - An approach to bring VLSI analog design to the hobbyists/non-professionals]]'', [https://www.eit.uni-kl.de/koenig/gemeinsame_seiten/projects/Research%20Projects.htm TU Kaiserslautern]<br />
* 11:30-12:00, Marie-Minerve Louërat, ''[[From filters to CMOS transistors - A library of analog schematics with automated sizing]]'', [https://www-soc.lip6.fr/en/team-cian/ LIP6]<br />
* 12:00-12:30, discussions<br><br><br />
* '''12:30-13:30''', '''lunch''' is served at the on-campus [http://www.locations.espaces.upmc.fr/fr/presentation_espaces/campus_jussieu/patio.html Le Patio]<br />
<br />
====Back-end design====<br />
* 13:30-14:30, [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], ''[[The Alliance/Coriolis design flow]]'', [https://www-soc.lip6.fr/equipe-cian/logiciels LIP6], '''(Tutorial)'''<br />
* 14:30-15:45, Matthias Köfferlein, ''[[Hands-on with KLayout: Design rule checks and layout to netlist tools]]'', [https://klayout.de KLayout], '''(Tutorial)'''<br />
* 15:45-16:00, conclusions<br />
<br />
== Practical information ==<br />
*[[FSiC2019 venue|Venue, map, hotels]]<br />
*[[FSiC2019 reimbursement|Trip and hotel reimbursement procedure]]<br />
*[[Guidelines for invited speakers]]<br />
*[[Mediawiki template for invited speakers]]<br />
<br />
==Supporting entities==<br />
[[File:LIP6_SU_CNRS_logo.jpg|500px]]</div>Coussyhttps://wiki.f-si.org/index.php?title=GAUT&diff=1800GAUT2019-03-06T07:58:19Z<p>Coussy: GAUT - A Free and Open-Source High-Level Synthesis tool</p>
<hr />
<div>GAUT is a free academic High-Level Synthesis (HLS) tool. Starting from a C/C++ input description and a set of synthesis options, GAUT automatically generates a hardware architecture composed of a controller and a datapath as well as memory and communication interfaces. GAUT generates IEEE P1076 compliant RTL level VHDL and SystemC projects. The VHDL files are inputs for off the shelf logical synthesis tools. Windows, Linux and MacOS platforms are supported (32 or 64 bits).<br />
This talk will introduce the main steps of HLS and give an overview of the GAUT tool (main features, architecture, short history and purpose).<br />
<br />
More information and download: www.gaut.fr</div>Coussy