FSiC2025
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| Free Silicon Conference 2025 | |
|---|---|
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| Genre | Free software and free hardware development conference |
| Location(s) | IHP Microelectronics, Frankfurt an der Oder |
| Country | Germany |
| Website | wiki.f-si.org/index.php/FSiC2025 |
The 2025 Free Silicon Conference (FSiC) will take place at IHP Microelectronics (Frankfurt an der Oder) on July 2, 3, 4 2025 (Wednesday to Friday). This event will build on top of the past FSiC editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification.
Submission
Submissions ended on May 1st.
Participation
To participate to the conference, both as speaker and as attendee, it is necessary to register. As of May 19, however, we have reached the maximum number of participants and registrations are closed.
Tentative program
July 2, Wednesday (day 1)
- 8:00, registration
- 8:30-9:00, early bird coffee and tea
Welcome
- 9:00, Gerhard Kahmen (Scientific director at IHP Microelectronics), Welcome and introduction of IHP
Digital design and logic-synthesis
- 9:10, Matthias Jung (University of Würzburg), DRAM simulation with the simulator DRAMSys
- 9:30, Edward Bingham (Broccolimicro), The potential for asynchronous circuits to bridge the hardware / software divide
- 9:50, Marcel Walter (TU Munich), aigverse: Toward machine learning-driven logic synthesis
- 10:10, Tjark Petersen (DTU), Towards open-source functional verification methodologies
- 10:30, Andreas Krall (TU Wien), OpenVADL: An open source implementation of the Vienna architecture description language
- 10:50, Kari Hepola and/or Joonas Multanen (Tampere University), Kactus2 (title to be announced)
- 11:10, Oscar Gustafsson (Linköping University), B-ASIC: a framework for simulation and implementation of static DSP algorithms
- 11:30, Pekka Jääskeläinen (Tampere University), OpenASIP: Co-processor co-design using open source tooling
- 11:50, Jasper Homann and Guillermo Payá Vayá (TU Braunschweig), Comprehensive functional verification of a configurable N-pipeline-stages RISC-V-based softcore orocessor using the PATARA framework (lightning talk)
- 12:00-13:30, lunch break
Foundries, PDKs and standard-cell libraries
- 13:30, Jun-Ichi Okamura (AIST Solutions), 5W1H: Open-source PDK from the perspective of Japanese foundries aka -other side of the moon-
- 13:50, Sergei Andreev (IHP Microelectronics), IHP Open PDK: development status updates and looking ahead
- 14:10, Dietmar Warning (IHP Microelectronics), Verilog-A models in IHP OpenPDK for a modern SiGe RF process
- 14:30, Marcus Mellor, (Infinitymdm), CharLib: an open-source standard-cell library characterizer
- 14:50, Shinichi Nishizawa, (Hiroshima University), libretto: An open-source library characterizer for open-source VLSI design
- 15:10, Charlotte Nägle (Bielefeld University), Open subthreshold standard-cell library for energy-efficient digital circuits (lightning talk)
- 15:30-16:00, coffee break
- 16:00-18:30, cleanroom and labs tour (3 stations, 3 groups, max 20 people/group)
- 18:30-20:00, dinner (barbecue & chips at IHP)
July 3, Thursday (day 2)
- 8:30-9:00, early bird coffee and tea
On-going FOS silicon projects
- 9:00, Leo Moser (formerly Efabless), Greyhound: A RISC-V SoC with tightly coupled eFPGA on IHP SG13G2
- 9:20, Simon Dorrer (Johannes Kepler University (JKU) Linz), Design of an open-source fully-differential adaptive event-based ADC for bio-signal acquisition in 130nm CMOS
- 9:40, Daniel Schultz, (ElemRV), ElemRV - Open source RISC-V microcontroller
- 10:00, Zachary Kohnen and Alex Alvarado (Eindhoven University of Technology), Manchester decoder of a home thermostat's wireless protocol in the Tiny Tapeout 07 shuttle (lightning talk)
- 10:20, Ghaith Al Sabagh (Johannes Kepler University (JKU) Linz), Open-source radar chip (lightning talk)
- 10:30, Tim Edwards (formerly Efabless, Open Circuit Design), Update on the Efabless "Frigate" next-generation harness chip, the "Panamax" padframe design, and results from the "Chipalooza" (lightning talk)
Analog flow, transistor modelling and circuit simulation
- 10:40, Arpad Buermen (University of Ljubljana), Recent developments in the Verilog-A circuit analysis kernel
- 11:00, Deni Alves (Federal University of Santa Catarina - Brasil), ACM2 – A MOSFET model bridging design and simulation
- 11:20, Volker Mühlhaus (Mühlhaus Consulting & Software GmbH), User friendly workflow for RFIC EM simulation using openEMS
- 11:40, Martin Köhler (Johannes Kepler University (JKU) Linz), KLayout-PEX
- 12:00-13:30, lunch break
- 13:30, Felix Salfelder (Gnucap MixedSignals), Progress on Verilog-AMS support in Gnucap
- 13:50, Leo Moser (formerly Efabless), Update on CACE (lightning talk)
- 14:00, Tobias Kaiser (TU Berlin), ORDeC: A text-driven analog IC design platform
- 14:20, Frans Skarman, (Linköping University), Surfer - an extensible and snappy waveform viewer
- 14:40, Holger Vogt (University Duisburg), ngspice - status update, and degradation simulation
Hardware security
- 15:00, Sebastian Haas (Barkhausen Institute), A secure hardware to enable trustworthy computing
- 15:30-16:00, coffee break
- 16:00, Christian Schulze (Agentur für Innovation in der Cybersicherheit GmbH (Cyberagentur)), Ecosystem verifably secure IT--provable cybersecurity
- 16:20, Simon Klix (Max Planck Institute for Security and Privacy), An introduction to hardware reverse engineering and HAL
Economic sustainability and hardware licences
- 16:40, Melanie Rieback (RadicallyOpenSecurity), Steward ownership and open silicon
- 17:00, Joaquin Matres Abril, Troy Tamas, Sebastian Goeldi, Floris Laporte, Jan David Fischbach and Matthew Mckee (GDSFactory), An open core model for EDA
- 17:20, Michael Weinberg (OSHWA), Martin Hauer (Open Source Ecology (OSE) Germany e.V.), Panel about hardware licences. Moderator: Panos Alevropoulos
- 18:00-19:00, shuttle to the city from IHP
- 19:00-20:00, city tour
- 20:00, dinner at Taverna Athos (at own expense)
July 4, Friday (day 3)
- 8:30-9:00, early bird coffee and tea
Policy, EU projects and funding opportunities
- 9:00, Krzysztof Herman (IHP Microelectronics), One year of experience with IHP OpenMPW shuttles: a review
- 9:20, Tina Tauchnitz (VDI/VDE-IT), Update on German Microelectronics Design Initiative
- 9:40, Norbert Herfurth (IHP Microelectronics), Towards industrial-grade designs with open-source EDA: The DI-FLOWSPACE and DI-SIGN-HEP Approach
Back-end design tools
- 10:00, Tim Edwards (formerly Efabless, Open Circuit Design), IHP Open PDK integration with Magic, Netgen, and Openlane2
- 10:20, Mohamed Gaber (The American University in Cairo), OpenLane: Looking to the future
- 10:40, Philippe Sauter and Thomas Benz (ETH Zurich), An open-source power simulation flow using OpenROAD
- 11:00, Joaquin Matres Abril, Troy Tamas, Sebastian Goeldi, Floris Laporte, Jan David Fischbach and Matthew Mckee (GDSFactory), GDSFactory+, the all-in-one solution for chip design
- 11:20, Philippe Sauter and Thomas Benz (ETH Zurich), ArtistIC: An open-source toolchain for top-metal IC art and ultra-high-fidelity GDSII renders
- 11:40, Peter Thoma (Frankfurt University of Applied Sciences), OpenTwin: An open-source framework for workflow orchestration with enhanced simulation and data management
- 12:00, Noam Cohen (KleperTech.io), Simplifying and accelerating EDA tool development with the NajaEDA Python library
- 12:20, Andrew Kahng (OpenROAD Initiative), Update on OpenROAD
- 13:00-13:30, lunch break (lunch bags to go)
Teaching and education
- 13:30, Zihao Yu and Xiaoke Su (Institute of Computing Technology, Chinese Academy of Sciences), "One Student One Chip" initiative: Learn to build RISC-V chips from scratch with MOOC
- 13:50, Yuchi Miao (Institute of Computing Technology, Chinese Academy of Sciences), Teaching open silicon design in a quarter
- 14:10, Kannan Moudgalya (Indian Institute of Technology Bombay), Open source EDA tool eSim for design and simulation, large scale training, and collaborative content creation
Standards
- 14:30, Dzmitry Pustakhod (Eindhoven University of Technology (TU/e)), R. Broeke, X. Leijtens, J. Matres Abril, P. Dumon, A. Schoenau, O. Abdeen, Y.D. Gupta, S. Latkowski, Photonic PDKs using openEPDA open standards: From foundry data to EPDA tools
- 14:50, Norbert Herfurth (IHP Microelectronics), The Transparent Reference Fab: A scalable, open blueprint for European semiconductor sovereignty
- 15:10, Christophe Alexandre (Naja), Open Source interchange format and data structures
- 15:30, Matthias Köfferlein (KLayout), It's time to reinvent the wheel - a plead for disruptive changes in the file format department
- 15:50, conclusions
Practical information
- Conference address:
IHP GmbH Leibniz Institute for High Performance Microelectronics/Leibniz-Institut für innovative Mikroelektronik Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
- Conference location on OpenStreetMap
- Accommodation and venue
Organizing committee
‟For democracy to thrive, technology must empower, not control.”
‟Technology is political. I stand for defending free access to technology and the right for transparency.”
‟Free and transparent technology empowers people and protects fundamental freedoms.”
Constantin Gierczak-Galle
Student and enthousiast
‟Technology can be both Mankind's development and demise. Promoting the former while hindering the latter can only happen through decentralization, democratization and open collaboration.”
‟I am passionate about helping people with my technical skills. Coding EDA is like gardening to me: may it grow and feed people.”
‟I like to understand technology, to adapt and enhance it. Technology should not be mythical or owned by experts only, it needs to be comprehensible.”
‟Open-source tools and technology gives freedom to students to explore chip design on their own and on their computers, not limiting them to the walled garden of a dedicated lab at the University.”
‟Our goal is to make open source EDA tools and design flows easily accessible and usable for anyone who wants to get into ASIC chip design, test new design ideas and develop them to a manufacturable level.”
Local hosting committee
The event is supported by members of IHP Microelectronics including Kerstin Kaslack, Jonas Linzert, Henriette Mohles, Anna Sojka-Piotrowska and Inesa Posypai.
Donations
We are looking for sponsors to cover extra services at the conference. In case of interest, please see the registration tab here.
Sponsors
Acknowledgements
This conference is co-funded by European Union through the Coordination and Support Action GoIT project with ID number 101070669. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or of the European Commission. Neither the European Union nor the European Commission can be held responsible for them.
This conference also received funding from the Swiss State Secretariat for Education, Research and Innovation (SERI) under the NGI0 Commons Fund project. The NGI0 Commons Fund has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No. 101135429.
